blob: 69aed97be2a69a5029f4bea0bd81bf25b81956ed [file] [log] [blame]
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# Configuration file for running experiments #
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# Path to directory of circuits to use
circuits_dir=benchmarks/blif
# Path to directory of architectures to use
archs_dir=arch/timing
# Add circuits to list to sweep
# Single-clock
circuit_list_add=bigkey.blif
circuit_list_add=clma.blif
circuit_list_add=diffeq.blif
circuit_list_add=dsip.blif
circuit_list_add=elliptic.blif
circuit_list_add=frisc.blif
circuit_list_add=s298.blif
circuit_list_add=s38417.blif
circuit_list_add=s38584.1.blif
circuit_list_add=tseng.blif
# Combinational
#circuit_list_add=alu4.blif
#circuit_list_add=apex2.blif
#circuit_list_add=apex4.blif
#circuit_list_add=des.blif
#circuit_list_add=ex1010.blif
#circuit_list_add=ex5p.blif
#circuit_list_add=misex3.blif
#circuit_list_add=pdc.blif
#circuit_list_add=seq.blif
#circuit_list_add=spla.blif
# Add architectures to list to sweep
arch_list_add=k6_frac_N10_40nm.xml
# Parse info and how to parse
parse_file=vpr_standard.txt
# How to parse QoR info
qor_parse_file=qor_standard.txt
# Pass requirements
pass_requirements_file=pass_requirements.txt
# Script parameters
script_params=-starting_stage abc