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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
86cd42e31d9cc53e26547986dbd428b78ec4ee52
/
.
/
libs
/
EXTERNAL
/
libblifparse
/
test
/
eblif
/
test.eblif
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.
model top
.
inputs a b clk
.
outputs o_dff
.
names a b a_and_b
11
1
.
cname lut_a_and_b
.
subckt dff \
d
=
a_and_b \
q
=
dff_q \
clk
=
clk
.
cname my_dff
.
conn dff_q o_dff
.
end
.
model dff
.
inputs d clk
.
outputs q
.
blackbox
.
end
