blob: 81e896c6280ea1f2a1c26e5e9167b99956227132 [file] [log] [blame]
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# Configuration file for running experiments
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script_params=-use_odin_simulation -use_new_latches_restoration_script -starting_stage abc
# Path to directory of circuits to use
circuits_dir=benchmarks/blif/multiclock
# Path to directory of architectures to use
archs_dir=arch/timing
# Add circuits to list to sweep (basic bm)
circuit_list_add=cascading_ff.blif
circuit_list_add=multiclock.blif
circuit_list_add=multiclock_output_and_latch.blif
circuit_list_add=multi_clock_reader_writer.blif
circuit_list_add=multiclock_reader_writer.blif
circuit_list_add=multiclock_separate_and_latch.blif
circuit_list_add=simple_multiclock.blif
# Add circuits to list to sweep (large bm)
circuit_list_add=iir1.blif
circuit_list_add=stereovision3.blif
circuit_list_add=sv_chip3_hierarchy_no_mem.blif
# Add architectures to list to sweep
arch_list_add=k6_frac_N10_mem32K_40nm.xml
# Parse info and how to parse
parse_file=vpr_standard.txt
# How to parse QoR info
qor_parse_file=qor_standard.txt
# Pass requirements
pass_requirements_file=pass_requirements.txt