vtr_flow/tasks/timing_small/config/config.txt

#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/verilog

# Path to directory of architectures to use
archs_dir=arch/timing

# Add circuits to list to sweep
#circuit_list_add=bgm.v
circuit_list_add=blob_merge.v
circuit_list_add=boundtop.v
circuit_list_add=ch_intrinsics.v
circuit_list_add=diffeq1.v
circuit_list_add=diffeq2.v
#circuit_list_add=LU8PEEng.v
#circuit_list_add=LU32PEEng.v
#circuit_list_add=LU64PEEng.v
#circuit_list_add=mcml.v
circuit_list_add=mkDelayWorker32B.v
circuit_list_add=mkPktMerge.v
circuit_list_add=mkSMAdapter4B.v
circuit_list_add=or1200.v
circuit_list_add=raygentop.v
circuit_list_add=sha.v
#circuit_list_add=stereovision0.v
#circuit_list_add=stereovision1.v
#circuit_list_add=stereovision2.v
#circuit_list_add=stereovision3.v

# Add architectures to list to sweep
arch_list_add=k6_frac_N10_mem32K_40nm.xml

# Parse info and how to parse
parse_file=vpr_standard.txt

# Pass requirements
pass_requirements_file=pass_requirements.txt

script_params=-lut_size 6