vtr_flow/benchmarks/blif/4/s208.blif

.model top
.inputs s208_in_10_ s208_in_1_ s208_in_0_ s208_in_3_ s208_in_2_ s208_in_5_ \
s208_in_4_ s208_in_7_ s208_in_6_ clock s208_in_9_ s208_in_8_
.outputs s208_out_1_ s208_out_0_
.latch    n_n23 n_n46 re clock 2
.latch    n_n24 n_n47 re clock 2
.latch    n_n25 n_n48 re clock 2
.latch    n_n26 n_n49 re clock 2
.latch    n_n27 n_n50 re clock 2
.names n_n48 n_n49 [117] s208_out_1_
001 1
.names s208_in_10_ [14] [120] s208_out_0_
11- 1
1-1 1
.names s208_in_10_ s208_in_9_ n_n46 n_n23
0-- 1
-1- 1
--0 1
.names s208_in_10_ s208_in_9_ n_n46 n_n47 n_n24
1001 1
1010 1
.names n_n46 n_n47 n_n48 [18] n_n25
0-11 1
-011 1
1101 1
.names [19] [23] [111] [112] n_n26
-11- 1
1--1 1
.names n_n48 n_n49 [19] [30] n_n27
---1 1
111- 1
.names s208_in_10_ s208_in_9_ [18]
10 1
.names s208_in_10_ s208_in_9_ n_n46 n_n47 [19]
1011 1
.names n_n46 n_n47 n_n48 [23]
0-- 1
-0- 1
--0 1
.names s208_in_3_ s208_in_4_ n_n48 n_n49 [22]
1-1- 1
-101 1
.names n_n46 n_n47 [22] [119] [14]
1--1 1
101- 1
.names s208_in_9_ n_n46 n_n50 [30]
001 1
.names s208_in_10_ s208_in_9_ n_n49 [111]
101 1
.names n_n49 n_n48 [112]
01 1
.names n_n46 n_n47 n_n50 [117]
000 1
.names s208_in_2_ s208_in_5_ n_n47 n_n50 [119]
1-1- 1
-1-1 1
.names s208_in_1_ s208_in_0_ n_n46 [120]
-1- 1
1-0 1
.end