vtr_flow/benchmarks/blif/4/s420.blif

.model top
.inputs s420_in_9_ s420_in_8_ s420_in_7_ s420_in_6_ s420_in_10_ s420_in_11_ \
s420_in_12_ s420_in_13_ s420_in_1_ s420_in_14_ s420_in_0_ s420_in_15_ \
s420_in_16_ s420_in_17_ s420_in_5_ s420_in_18_ s420_in_4_ s420_in_3_ \
s420_in_2_ clock
.outputs s420_out_1_ s420_out_0_
.latch    n_n23 n_n55 re clock 2
.latch    n_n24 n_n56 re clock 2
.latch    n_n25 n_n57 re clock 2
.latch    n_n26 n_n58 re clock 2
.latch    n_n27 n_n59 re clock 2
.names n_n55 n_n56 n_n57 n_n59 s420_out_1_
0000 1
.names s420_in_18_ n_n55 [14] [191] s420_out_0_
1--1 1
111- 1
.names s420_in_17_ s420_in_18_ n_n55 n_n23
1-- 1
-0- 1
--0 1
.names n_n23 [29] [28] [177] n_n24
0-1- 1
-1-1 1
.names n_n23 [31] [30] [180] n_n25
0-1- 1
-1-1 1
.names n_n23 [46] [183] n_n26
-1- 1
0-1 1
.names n_n23 [33] [184] [185] n_n27
01-- 1
--11 1
.names s420_in_18_ n_n57 n_n59 [29]
1-- 1
-10 1
.names n_n56 n_n57 n_n58 n_n59 [28]
01-- 1
-1-1 1
0-01 1
.names s420_in_18_ n_n55 n_n56 n_n59 [31]
10-- 1
1-11 1
-010 1
1-00 1
.names n_n56 n_n57 n_n58 n_n59 [30]
--1- 1
10-0 1
.names n_n56 n_n57 n_n59 [33]
00- 1
-10 1
.names s420_in_3_ s420_in_2_ n_n56 n_n59 [35]
1-11 1
-101 1
-110 1
.names n_n57 [35] [189] [190] [14]
01-- 1
1-1- 1
1--1 1
.names s420_in_17_ s420_in_18_ n_n55 n_n58 [46]
0101 1
.names s420_in_17_ n_n55 n_n56 [177]
001 1
.names n_n57 s420_in_17_ [180]
10 1
.names n_n56 n_n57 n_n59 [183]
101 1
.names s420_in_18_ s420_in_17_ [184]
10 1
.names n_n55 n_n57 n_n59 [185]
0-1 1
-01 1
.names s420_in_4_ s420_in_3_ n_n56 n_n59 [189]
1-01 1
-100 1
.names s420_in_5_ s420_in_2_ n_n56 n_n59 [190]
-111 1
1-10 1
.names s420_in_1_ s420_in_0_ n_n55 [191]
-1- 1
1-0 1
.end