Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
8d73e272f53eecfcbc9525001dddd622c86aee97
/
.
/
vtr_flow
/
benchmarks
/
blif
/
7
/
shiftreg.blif
blob: 1c43fc140e4a397add9a8992342d042006a08bcf [
file
] [
log
] [
blame
]
.
model top
.
inputs shiftreg_in clock
.
outputs shiftreg_out
.
latch shiftreg_in n_n10 re clock
2
.
latch n_n10 n_n11 re clock
2
.
latch n_n11 shiftreg_out re clock
2
.
end
