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vtr-verilog-to-routing
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8ef7e7d8c05b3a1de4d7768c6d85d15322753ba6
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abc_with_bb_support
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simple.resyn.blif
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# Benchmark "simple" written by ABC on Mon Mar 28 13:44:30 2011
.
model simple
.
inputs top
^
clock top
^
enable
.
outputs top
^
value_out
.
latch n7 top
^
FF_NODE
~
3
0
.
names top
^
enable top
^
FF_NODE
~
3
n7
01
1
.
names top
^
FF_NODE
~
3
top
^
value_out
1
1
.
end
