| vpr_status;output.txt;vpr_status=(.*) |
| min_chan_width;vpr.out;Best routing used a channel width factor of (\d+) |
| critical_path_delay;vpr.crit_path.out;Final critical path: (.*) ns |
| routed_wirelength;vpr.out;Total wirelength: (.*), average |
| pack_time;vpr.out;Packing took (.*) seconds |
| place_time;vpr.out;Placement took (.*) seconds |
| min_chan_width_route_time;vpr.out;Routing took (.*) seconds |
| crit_path_route_time;vpr.crit_path.out;Routing took (.*) seconds |
| num_pre_packed_nets;vpr.out;total nets: (\d+) |
| num_pre_packed_blocks;vpr.out;total blocks: (\d+) |
| num_post_packed_nets;vpr.out;Netlist num_nets:\s*(\d+) |
| num_clb;vpr.out;Netlist clb blocks:\s*(\d+) |
| num_io;vpr.out;Netlist inputs pins:\s*(\d+) |
| num_outputs;vpr.out;Netlist output pins:\s*(\d+) |
| num_memories;vpr.out;Netlist memory blocks:\s*(\d+) |
| num_mult;vpr.out;Netlist mult_36 blocks:\s*(\d+) |
| total_power;*.power;^Total\s+(.*?)\s+ |
| routing_power_perc;*.power;^\s+Routing\s+\S+\s+(.*?)\s+ |
| clock_power_perc;*.power;^\s+Clock\s+\S+\s+(.*?)\s+ |
| tile_power_perc;*.power;^\s+PB Types\s+\S+\s+(.*?)\s+ |
| error;output.txt;error=(.*) |
| |
