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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
9f7c0672ba4f058e09bab2d0efa43570890ad268
/
.
/
vtr_flow
/
benchmarks
/
microbenchmarks
/
and_latch.blif
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.
model top
.
inputs a b clk
.
outputs
out
.
names a b c
11
1
.
latch c
out
re clk
0
.
end
