libs/EXTERNAL/libsdcparse/golden.log

File: ../test_sdcs/test.sdc
Line   3: create_clock -period 3.000000 -waveform {1.250000 2.750000} {clk0}
Line   4: create_clock -period 3.000000 -waveform {1.000000 2.000000} {clk1}
Line   5: create_clock -period 2.300000 -waveform {0.000000 1.150000} {clk2}
Line   7: create_clock -period 2.000000 -waveform {0.000000 1.000000} {clk3 clk4}
Line   9: create_clock -period 1.000000 -waveform {0.000000 0.500000} -name input_clk
Line  11: create_clock -period 0.000000 -waveform {0.000000 0.000000} -name output_clk
Line  35: set_input_delay -clock input_clk -max 0.500000 [get_ports {in1 in2 in3}]
Line  37: set_output_delay -clock output_clk -max 1.000000 [get_ports {out*}]
Line  41: set_output_delay -clock eof_test -max 1.729300 [get_ports {eof_test_port*}]
Line  13: set_clock_groups  -exclusive -group {input_clk} -group {clk2} -group [get_clocks {clk3}]
Line  15: set_clock_groups  -exclusive -group {input_clk input_clock2} -group {clk2} -group [get_clocks {asdf qwerty}]
Line  17: set_false_path -from [get_clocks {clk}] -to [get_clocks {output_clk}]
Line  18: set_false_path -from {asdf~/ff} -to {wer/234/ff3 xcw/32|ff2}
Line  19: set_false_path -from {asdf/ff qwert/asd/ff} -to [get_clocks {output_clk}]
Line  21: set_false_path -from [get_clocks {output_clk}] -to {asdf/ff2}
Line  23: set_max_delay 2.000000 -from [get_clocks {clk}] -to [get_clocks {output_clk}]
Line  24: set_max_delay 3.600000 -from {asdf~/ff} -to {wer/234/ff3 xcw/32|ff2}
Line  25: set_max_delay 0.300000 -from {asdf/ff qwert/asd/ff} -to [get_clocks {output_clk}]
Line  27: set_max_delay 0.000000 -from [get_clocks {output_clk}] -to {asdf/ff2}
Line  29: set_multicycle_path 2 -setup -from [get_clocks {clk}] -to [get_clocks {output_clk}]
Line  30: set_multicycle_path 3 -setup -from {asdf~/ff} -to {wer/234/ff3 xcw/32|ff2}
Line  31: set_multicycle_path 3 -setup -from {asdf/ff qwert/asd/ff} -to [get_clocks {output_clk}]
Line  33: set_multicycle_path 0 -setup -from [get_clocks {output_clk}] -to {asdf/ff2}

File: ../test_sdcs/test5.sdc
Line   1: create_clock -period 0.000000 -waveform {0.000000 0.000000} {*}

File: ../test_sdcs/test2.sdc
Line  12: create_clock -period 1.000000 -waveform {0.000000 0.500000} -name virtual_io_clock
Line  13: create_clock -period 1.000000 -waveform {0.000000 0.500000} {clk0}
Line  14: create_clock -period 1.000000 -waveform {0.000000 0.500000} {a[0]}
Line  16: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_minres:inst_pll_minres|altpll:altpll_component|pll_minres_altpll:auto_generated|wire_pll1_clk[0]}
Line  26: set_input_delay -clock virtual_io_clock -max 0.000000 [get_ports {*}]
Line  31: set_output_delay -clock virtual_io_clock -max 0.000000 [get_ports {*}]
Line  35: set_clock_groups  -exclusive -group {clk0} -group {pll_minres:inst_pll_minres|altpll:altpll_component|pll_minres_altpll:auto_generated|wire_pll1_clk[0]}

File: ../test_sdcs/test3.sdc
Line  12: create_clock -period 1.000000 -waveform {0.000000 0.500000} -name virtual_io_clock
Line  13: create_clock -period 1.000000 -waveform {0.000000 0.500000} {clk}
Line  14: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type0:\using_pll:separate_clk:noc_pll_0|altpll:altpll_component|pll_noc_type0_altpll:auto_generated|wire_pll1_clk[0]}
Line  15: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type1:\using_pll:use_noc_pll_1:noc_pll_1|altpll:altpll_component|pll_noc_type1_altpll:auto_generated|wire_pll1_clk[0]}
Line  16: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type2:\using_pll:use_noc_pll_2:noc_pll_2|altpll:altpll_component|pll_noc_type2_altpll:auto_generated|wire_pll1_clk[0]}
Line  17: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type5:\using_pll:use_noc_pll_5:noc_pll_5|altpll:altpll_component|pll_noc_type5_altpll:auto_generated|wire_pll1_clk[0]}
Line  18: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type4:\using_pll:use_noc_pll_4:noc_pll_4|altpll:altpll_component|pll_noc_type4_altpll:auto_generated|wire_pll1_clk[0]}
Line  19: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type3:\using_pll:use_noc_pll_3:noc_pll_3|altpll:altpll_component|pll_noc_type3_altpll:auto_generated|wire_pll1_clk[0]}
Line  20: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type6:\using_pll:use_noc_pll_6:noc_pll_6|altpll:altpll_component|pll_noc_type6_altpll:auto_generated|wire_pll1_clk[0]}
Line  22: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll_noc_type7:\using_pll:use_noc_pll_7:noc_pll_7|altpll:altpll_component|pll_noc_type7_altpll:auto_generated|wire_pll1_clk[0]}
Line  32: set_input_delay -clock virtual_io_clock -max 0.000000 [get_ports {*}]
Line  37: set_output_delay -clock virtual_io_clock -max 0.000000 [get_ports {*}]
Line  41: set_clock_groups  -exclusive -group {clk} -group {pll_noc_type0:\using_pll:separate_clk:noc_pll_0|altpll:altpll_component|pll_noc_type0_altpll:auto_generated|wire_pll1_clk[0]} -group {pll_noc_type1:\using_pll:use_noc_pll_1:noc_pll_1|altpll:altpll_component|pll_noc_type1_altpll:auto_generated|wire_pll1_clk[0]} -group {pll_noc_type2:\using_pll:use_noc_pll_2:noc_pll_2|altpll:altpll_component|pll_noc_type2_altpll:auto_generated|wire_pll1_clk[0]} -group {pll_noc_type5:\using_pll:use_noc_pll_5:noc_pll_5|altpll:altpll_component|pll_noc_type5_altpll:auto_generated|wire_pll1_clk[0]} -group {pll_noc_type4:\using_pll:use_noc_pll_4:noc_pll_4|altpll:altpll_component|pll_noc_type4_altpll:auto_generated|wire_pll1_clk[0]} -group {pll_noc_type3:\using_pll:use_noc_pll_3:noc_pll_3|altpll:altpll_component|pll_noc_type3_altpll:auto_generated|wire_pll1_clk[0]} -group {pll_noc_type6:\using_pll:use_noc_pll_6:noc_pll_6|altpll:altpll_component|pll_noc_type6_altpll:auto_generated|wire_pll1_clk[0]} -group {pll_noc_type7:\using_pll:use_noc_pll_7:noc_pll_7|altpll:altpll_component|pll_noc_type7_altpll:auto_generated|wire_pll1_clk[0]}

File: ../test_sdcs/test4.sdc
Line  12: create_clock -period 1.000000 -waveform {0.000000 0.500000} -name virtual_io_clock
Line  13: create_clock -period 1.000000 -waveform {0.000000 0.500000} {pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]}
Line  15: create_clock -period 1.000000 -waveform {0.000000 0.500000} {OSC_CLK}
Line  25: set_input_delay -clock virtual_io_clock -max 0.000000 [get_ports {*}]
Line  30: set_output_delay -clock virtual_io_clock -max 0.000000 [get_ports {*}]
Line  34: set_clock_groups  -exclusive -group {pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]} -group {OSC_CLK}

File: ../test_sdcs/test7.sdc
Line   2: create_clock -period 3.000000 -waveform {1.250000 2.750000} {clk}
Line   3: create_clock -period 2.000000 -waveform {0.000000 1.000000} {clk2 clk_extra}
Line   4: create_clock -period 1.000000 -waveform {0.000000 0.500000} -name input_clk
Line   5: create_clock -period 0.000000 -waveform {0.000000 0.000000} -name output_clk
Line  10: set_input_delay -clock input_clk -max 0.500000 [get_ports {in1 in2 in3}]
Line  12: set_output_delay -clock output_clk -max 1.000000 [get_ports {out*}]
Line   6: set_clock_groups  -exclusive -group {input_clk} -group {clk2}
Line   7: set_false_path -from [get_clocks {clk}] -to [get_clocks {output_clk}]
Line   8: set_max_delay 17.000000 -from [get_clocks {input_clk}] -to [get_clocks {output_clk}]
Line   9: set_multicycle_path 5 -setup -from [get_clocks {clk}] -to [get_clocks {clk2}]

File: ../test_sdcs/test_invalid.sdc
Custom Error at line 2 near '-max': syntax error, unexpected -max, expecting -from or -to or end-of-line
Custom Error at line 0 near '': SDC Error: file failed to parse!


File: ../test_sdcs/test6.sdc
Line   2: create_clock -period 3.000000 -waveform {1.250000 2.750000} {clk}
Line   3: create_clock -period 2.000000 -waveform {0.000000 1.000000} {clk2}
Line   4: create_clock -period 2.500000 -waveform {0.000000 1.250000} -name virtual_io_clock
Line   5: set_input_delay -clock virtual_io_clock -max 1.000000 [get_ports {*}]
Line   6: set_output_delay -clock virtual_io_clock -max 0.500000 [get_ports {*}]