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foss-fpga-tools
/
third_party
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vtr-verilog-to-routing
/
a2c37c91c9836429efe18a8bd6fd68bc656e32b7
/
.
/
vtr_flow
/
sdc
/
samples
/
stereovision3.sdc
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create_clock
-
period
10
*
set_clock_latency
-
source
2
-
late
[
get_clocks
{
clk
}]
