blob: 9f4424a60d07a246541f850db355e18aaee5887d [file] [log] [blame]
##############################################
# Configuration file for running experiments
##############################################
script_params=-power
cmos_tech_behavior=PTM_45nm/45nm.xml
# Path to directory of circuits to use
circuits_dir=benchmarks/verilog
# Path to directory of architectures to use
archs_dir=arch/power
# Add circuits to list to sweep
circuit_list_add=bgm.v
circuit_list_add=blob_merge.v
circuit_list_add=boundtop.v
circuit_list_add=ch_intrinsics.v
circuit_list_add=diffeq1.v
circuit_list_add=diffeq2.v
circuit_list_add=LU8PEEng.v
circuit_list_add=LU32PEEng.v
#circuit_list_add=LU64PEEng.v
circuit_list_add=mcml.v
circuit_list_add=mkDelayWorker32B.v
circuit_list_add=mkPktMerge.v
circuit_list_add=mkSMAdapter4B.v
circuit_list_add=or1200.v
circuit_list_add=raygentop.v
circuit_list_add=sha.v
circuit_list_add=stereovision0.v
circuit_list_add=stereovision1.v
circuit_list_add=stereovision2.v
#circuit_list_add=stereovision3.v
# Add architectures to list to sweep
arch_list_add=k6_N10_I40_Fi6_L4_frac0_ff1_45nm.xml
# Parse info and how to parse
parse_file=vpr_power_detailed.txt
# Pass requirements
pass_requirements_file=pass_requirements.txt