vtr_flow/benchmarks/microbenchmarks/rca_2bit.blif - third_party/vtr-verilog-to-routing - Git at Google

 .model top
 .inputs cin a0 a1 b0 b1
 .outputs s0 s1 cout
 .names cin a0 a1 b0 b1 s1
 000-1 1
 001-0 1
 0-001 1
 0-100 1
 110-0 1
 111-1 1
 1-010 1
 1-111 1
 -0001 1
 -0100 1
 -1010 1
 -1111 1
 .names cin a0 b0 s0
 001 1
 010 1
 100 1
 111 1
 .names cin a0 a1 b0 b1 cout
 111-- 1
 11--1 1
 1-11- 1
 1--11 1
 -111- 1
 -1-11 1
 --1-1 1
 .end
	.model top
	.inputs cin a0 a1 b0 b1
	.outputs s0 s1 cout
	.names cin a0 a1 b0 b1 s1
	000-1 1
	001-0 1
	0-001 1
	0-100 1
	110-0 1
	111-1 1
	1-010 1
	1-111 1
	-0001 1
	-0100 1
	-1010 1
	-1111 1
	.names cin a0 b0 s0
	001 1
	010 1
	100 1
	111 1
	.names cin a0 a1 b0 b1 cout
	111-- 1
	11--1 1
	1-11- 1
	1--11 1
	-111- 1
	-1-11 1
	--1-1 1
	.end