ODIN_II/REGRESSION_TESTS/BENCHMARKS/BUGS/README - third_party/vtr-verilog-to-routing - Git at Google

 Nomemory Runs and compiles


 The instantiation of memory seems to form a combinational
 loop in memory_combinational.v

 THe main difference is that in the memory one the sign extender module's input is not primary, but from the output of the memory.
	Nomemory Runs and compiles


	The instantiation of memory seems to form a combinational
	loop in memory_combinational.v

	THe main difference is that in the memory one the sign extender module's input is not primary, but from the output of the memory.