ODIN_II/REGRESSION_TESTS/BENCHMARKS/BUGS/file_two.v - third_party/vtr-verilog-to-routing - Git at Google

 module testmodule (a,b,c);

 input [31:0] a;
 input [31:0] b;
 output [31:0] c;

 assign c = a & b;

 endmodule
	module testmodule (a,b,c);

	input [31:0] a;
	input [31:0] b;
	output [31:0] c;

	assign c = a & b;

	endmodule