vtr_flow/arch/timing/soft_fpu_arch_timing.xml

<!-- Use Virtex II-like architecture  N04K04L04.FC15FO25.AREA1DELAY1.CMOS130NM.BPTM     Width = 72 -->
  
  <architecture>


  
  <!-- ODIN II specific config -->
  <models>


 
  </models>
  <!-- ODIN II specific config ends -->
 
  <!-- Physical descriptions begin (area optimized for N8-K6-L4 -->
  <layout auto="1.0"/>
		<device>
			<sizing R_minW_nmos="2800.310059" R_minW_pmos="7077.009766" ipin_mux_trans_size="1.221260"/>
			<timing C_ipin_cblock="0.000000e+00" T_ipin_cblock="8.607000e-11"/>
			<area grid_logic_tile_area="2292.209961"/>
			<chan_width_distr>
				<io width="1.000000"/>
				<x distr="uniform" peak="1.000000"/>
				<y distr="uniform" peak="1.000000"/>
			</chan_width_distr>
			<switch_block type="wilton" fs="3"/>
		</device>
		<switchlist>
			<switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="1.102000e-10" mux_trans_size="1.214940" buf_size="11.910600"/>
		</switchlist>
		<segmentlist>
			<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
			<mux name="0"/>
			<sb type="pattern">1 1 1 1 1</sb>
			<cb type="pattern">1 1 1 1</cb>
			</segment>
		</segmentlist>

		<complexblocklist>
      <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
      <pb_type name="io" capacity="3">
        <input name="outpad" num_pins="1"/>
        <output name="inpad" num_pins="1"/>
        <clock name="clock" num_pins="1"/>

        <!-- IOs can operate as either inputs or outputs -->
        <mode name="inpad">
          <pb_type name="inpad" blif_model=".input" num_pb="1">
            <output name="inpad" num_pins="1"/>
          </pb_type>
          <interconnect>
            <direct name="inpad" input="inpad.inpad" output="io.inpad">
            <delay_constant max="9.762000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
            </direct>
          </interconnect>
      
        </mode>
        <mode name="outpad">
          <pb_type name="outpad" blif_model=".output" num_pb="1">
            <input name="outpad" num_pins="1"/>
          </pb_type>
          <interconnect>
            <direct name="outpad" input="io.outpad" output="outpad.outpad">
            <delay_constant max="2.700000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
            </direct>
          </interconnect>
        </mode>

				<fc_in type="frac">1.000000</fc_in>
				<fc_out type="frac">0.250000</fc_out>

        <!-- IOs go on the periphery of the FPGA, for consistency, 
          make it physically equivalent on all sides so that only one definition of I/Os is needed.
          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
        -->
        <pinlocations pattern="custom">
          <loc side="left">io.outpad io.inpad io.clock</loc>
          <loc side="top">io.outpad io.inpad io.clock</loc>
          <loc side="right">io.outpad io.inpad io.clock</loc>
          <loc side="bottom">io.outpad io.inpad io.clock</loc>
        </pinlocations>

        <gridlocations>
          <loc type="perimeter" priority="10"/>
        </gridlocations>

      </pb_type>
      <!-- Describe general-purpose complex block -->
      <pb_type name="clb">        
          <input name="I" num_pins="10" equivalent="true"/>
          <output name="O" num_pins="4" equivalent="true"/>
          <clock name="clk" num_pins="1"/>
          <pb_type name="ble" num_pb="4">
             <input name="in" num_pins="4"/>
             <output name="out" num_pins="1"/>
             <clock name="clk" num_pins="1"/>
             <pb_type name="soft_logic" num_pb="1">
               <input name="in" num_pins="4"/>
               <output name="out" num_pins="1"/>
            <mode name="n1_lut4">
              <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
                <input name="in" num_pins="4" port_class="lut_in"/>
                <output name="out" num_pins="1" port_class="lut_out"/>
                <!-- LUT timing using delay matrix -->
                <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
                  2.581000e-10
                  2.581000e-10
                  2.581000e-10
                  2.581000e-10
                </delay_matrix>
              </pb_type>
              <interconnect>
                <direct name="direct1" input="soft_logic.in[3:0]" output="lut4[0:0].in[3:0]"/>
                <direct name="direct2" input="lut4[0:0].out" output="soft_logic.out[0:0]"/>
              </interconnect>
            </mode>
             </pb_type>
          <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
            <input name="D" num_pins="1" port_class="D"/>
            <output name="Q" num_pins="1" port_class="Q"/>
            <clock name="clk" num_pins="1" port_class="clock"/>
            <T_setup value="2.359000e-10" port="ff.D" clock="clk"/>
            <T_clock_to_Q max="1.508000e-10" port="ff.Q" clock="clk"/>
          </pb_type>
            <interconnect>
              <direct name="direct1" input="soft_logic.out[0:0]" output="ff.D"/>
              <direct name="direct2" input="ble.in" output="soft_logic.in"/>
              <direct name="direct3" input="ble.clk" output="ff.clk"/>
              <mux name="mux1" input="ff.Q soft_logic.out[0:0]" output="ble.out[0:0]"/>
             </interconnect>
          </pb_type>

          <interconnect>
            <complete name="complete1" input="clb.I ble[3:0].out" output="ble[3:0].in">
              <delay_constant max="7.586000e-11" in_port="clb.I" out_port="ble[3:0].in" />
              <delay_constant max="7.260000e-11" in_port="ble[3:0].out" out_port="ble[3:0].in" />
            </complete>
            <complete name="complete2" input="clb.clk" output="ble[3:0].clk"/>
            <direct name="direct1" input="ble[3:0].out" output="clb.O"/>
          </interconnect>
				<fc_in type="frac">0.150000</fc_in>
				<fc_out type="frac">0.250000</fc_out>
        <pinlocations pattern="spread"/>
        <gridlocations>
          <loc type="fill" priority="1"/>
        </gridlocations>
      </pb_type>
    </complexblocklist>
  </architecture>