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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
bed3849427d1fcaec7c466a8326a30232278323b
/
.
/
libs
/
EXTERNAL
/
libsdcparse
/
test_sdcs
/
test13.sdc
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set_clock_latency
-
source
-
late
3.4
[
get_clocks clk1
]
set_clock_latency
-
source
-
late
3.4
[
get_clocks clk
*]
set_clock_latency
-
source
-
early
3.4
[
get_clocks
{
clk2
}]
set_clock_latency
-
source
3.4
[
get_clocks
{
clk3
}]
