vtr_flow/parse/parse_config/vpr_standard.txt

#General
vpr_revision;vpr.out;Revision:\s(.*);unknown
vpr_status;output.txt;vpr_status=(.*)
error;output.txt;error=(.*)

#VPR Netlist statistics
num_pre_packed_nets;vpr.out;\s*Nets\s*:\s*(\d+)
num_pre_packed_blocks;vpr.out;\s*Blocks\s*:\s*(\d+)

#VPR Packing Metrics
num_post_packed_nets;vpr.out;Netlist num_nets:\s*(\d+)
num_post_packed_blocks;vpr.out;Netlist num_blocks:\s*(\d+)
device_width;vpr.out;FPGA sized to (\d+) x \d+
device_height;vpr.out;FPGA sized to \d+ x (\d+)

#VTR benchmark packing metrics
num_clb;vpr.out;Netlist clb blocks:\s*(\d+)
num_io;vpr.out;Netlist inputs pins:\s*(\d+)
num_outputs;vpr.out;Netlist output pins:\s*(\d+)
num_memories;vpr.out;Netlist memory blocks:\s*(\d+)
num_mult;vpr.out;Netlist mult_36 blocks:\s*(\d+)

#VPR Place Metrics
placed_wirelength_est;vpr.out;BB estimate of min-dist \(placement\) wire length: (\d+)
placed_CPD_est;vpr.out;Placement estimated critical path delay: (.*) ns
placed_setup_TNS_est;vpr.out;Placement estimated setup Total Negative Slack \(sTNS\): (.*) ns
placed_setup_WNS_est;vpr.out;Placement estimated setup Worst Negative Slack \(sWNS\): (.*) ns

#VPR Min W Routing Metrics
min_chan_width;vpr.out;Best routing used a channel width factor of (\d+)
routed_wirelength;vpr.out;Total wirelength: (.*), average
min_chan_width_route_success_iteration;vpr.out;Successfully routed after (\d+) routing iterations

#VPR Critical Path Routing Metrics
crit_path_routed_wirelength;vpr.crit_path.out;Total wirelength: (.*), average
crit_path_route_success_iteration;vpr.crit_path.out;Successfully routed after (\d+) routing iterations

#VPR Analysis (final implementation) Metrics
critical_path_delay;vpr.crit_path.out;Final critical path: (.*) ns
setup_TNS;vpr.crit_path.out;Setup Total Negative Slack \(sTNS\): (.*) ns
setup_WNS;vpr.crit_path.out;Setup Worst Negative Slack \(sWNS\): (.*) ns
hold_TNS;vpr.crit_path.out;Hold Total Negative Slack \(hTNS\): (.*) ns
hold_WNS;vpr.crit_path.out;Hold Worst Negative Slack \(hWNS\): (.*) ns

#Area Metrics
logic_block_area_total;vpr.out;Total logic block area .*: (.*)
logic_block_area_used;vpr.out;Total used logic block area: (.*)
min_chan_width_routing_area_total;vpr.out;Total routing area: (.*), per logic tile: .*
min_chan_width_routing_area_per_tile;vpr.out;Total routing area: .*, per logic tile: (.*)
crit_path_routing_area_total;vpr.crit_path.out;Total routing area: (.*), per logic tile: .*
crit_path_routing_area_per_tile;vpr.crit_path.out;Total routing area: .*, per logic tile: (.*)

#VPR Run-time Metrics
pack_time;vpr.out;Packing took (.*) seconds
place_time;vpr.out;Placement took (.*) seconds
min_chan_width_route_time;vpr.out;Routing took (.*) seconds
crit_path_route_time;vpr.crit_path.out;Routing took (.*) seconds

#Memory usage
max_vpr_mem;vpr.out;Maximum resident set size \(kbytes\): (\d+)
max_odin_mem;odin.out;Maximum resident set size \(kbytes\): (\d+)
max_abc_mem;abc.out;Maximum resident set size \(kbytes\): (\d+)