| arch circuit vpr_revision vpr_status min_chan_width critical_path_delay pack_time place_time min_chan_width_route_time crit_path_route_time routed_wirelength max_odin_mem max_abc_mem max_vpr_mem num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_clb num_io num_outputs num_memories num_mult error | |
| k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v a3a7317 success 48 3.83926 0.888154 0.48 0.69 0.07 4682 -1 -1 -1 765 895 415 36 99 130 1 0 |