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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
d1655d30c507a855f0430f81cd527d28456aa9b1
/
.
/
abc_with_bb_support
/
JAMIESON_TESTS
/
sample3.blif
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.
model
Adder02
.
inputs a00 a01
.
outputs y00
.
subckt FA a
=
a00 b
=
a01 cout
=
y00
.
end
.
model FA
.
inputs a b
.
outputs cout
.
names a b cout
11
1
.
end
