| arch circuit vpr_revision vpr_status error num_pre_packed_nets num_pre_packed_blocks num_post_packed_nets num_post_packed_blocks device_width device_height num_clb num_io num_outputs num_memories num_mult placed_wirelength_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration crit_path_routed_wirelength crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile crit_path_routing_area_total crit_path_routing_area_per_tile odin_synth_time abc_synth_time abc_cec_time abc_sec_time ace_time pack_time place_time min_chan_width_route_time crit_path_route_time vtr_flow_elapsed_time max_vpr_mem max_odin_mem max_abc_mem |
| k6_N10_mem32K_40nm.xml ch_intrinsics.v 30d086154 success 419 549 297 254 10 10 24 99 130 1 0 2221 2.62528 -243.1 -2.62528 44 1941 18 1755 17 3.02966 -286.064 -3.02966 0 0 3.92691e+06 1.84146e+06 235874. 2358.74 307351. 3073.51 0.03 0.01 -1 -1 -1 0.11 0.27 0.63 0.07 1.67 25272 9284 36400 |
| k6_N10_mem32K_40nm.xml diffeq1.v 30d086154 success 1001 938 713 312 16 16 49 162 96 0 5 10746 19.7499 -1523.89 -19.7499 50 10835 24 9313 26 21.7518 -1689.63 -21.7518 0 0 1.21132e+07 4.62081e+06 746321. 2915.31 990901. 3870.71 0.02 0.01 -1 -1 -1 0.30 0.82 2.63 0.61 5.09 38284 8328 37216 |
