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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
e3ba50265c283643ce235ed2fba66f678da0124a
/
.
/
libs
/
EXTERNAL
/
libsdcparse
/
test_sdcs
/
test_invalid.sdc
blob: 2568e524410701890867ae28263e502fa2806ce1 [
file
]
#False Path
set_false_path
-
from
[
get_clocks
{
clk
}]
-
max
