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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
e40bcd3e829b605fae7f076bd0ae2e7bdd76baf0
/
.
/
libs
/
EXTERNAL
/
libsdcparse
/
test_sdcs
/
test_early_late.sdc
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#Latency
set_clock_latency
-
source
-
early
-
late
3.4
[
get_clocks clk
*]
set_clock_latency
-
source
3.4
[
get_clocks clk
*]
#Derate
set_timing_derate
0.9
set_timing_derate
-
early
-
late
0.9
