Sign in
foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
e5087c33127e1c508ac36641c9dd302dcbf44b67
/
.
/
libs
/
EXTERNAL
/
libtatum
/
test
/
basic
/
simplest.single_clock.blif
blob: 98cfffca05e5326a01d557dbbf700c75b8c73d7e [
file
] [
log
] [
blame
]
.
model top
.
inputs a clk
.
outputs b
.
latch a l_a re clk
0
.
names l_a buf_l_a
1
1
.
latch buf_l_a b re clk
0
.
end
