vtr_flow/benchmarks/blif/2/s208.blif

.model top
.inputs s208_in_10_ s208_in_1_ s208_in_0_ s208_in_3_ s208_in_2_ s208_in_5_ \
s208_in_4_ s208_in_7_ s208_in_6_ clock s208_in_9_ s208_in_8_
.outputs s208_out_1_ s208_out_0_
.latch    n_n23 n_n46 re clock 2
.latch    n_n24 n_n47 re clock 2
.latch    n_n25 n_n48 re clock 2
.latch    n_n26 n_n49 re clock 2
.latch    n_n27 n_n50 re clock 2
.names [116] [117] s208_out_1_
11 1
.names s208_in_10_ [20] s208_out_0_
11 1
.names n_n46 [18] n_n23
0- 1
-0 1
.names [35] [36] n_n24
1- 1
-1 1
.names [33] [34] n_n25
1- 1
-1 1
.names [31] [32] n_n26
1- 1
-1 1
.names [29] [30] n_n27
1- 1
-1 1
.names [14] [120] [20]
1- 1
-1 1
.names s208_in_10_ s208_in_9_ [18]
10 1
.names n_n23 n_n47 [19]
01 1
.names n_n48 [110] [23]
0- 1
-1 1
.names n_n46 n_n47 [24]
0- 1
-0 1
.names [17] [119] [21]
1- 1
-1 1
.names [27] [28] [22]
1- 1
-1 1
.names n_n46 [21] [14]
11 1
.names s208_in_1_ n_n46 [15]
10 1
.names n_n47 [22] [17]
01 1
.names s208_in_5_ n_n50 [25]
11 1
.names s208_in_2_ n_n47 [26]
11 1
.names n_n49 [118] [27]
11 1
.names s208_in_3_ n_n48 [28]
11 1
.names [19] [113] [29]
11 1
.names n_n50 [114] [30]
11 1
.names [23] [111] [31]
11 1
.names [19] [112] [32]
11 1
.names [24] [109] [33]
11 1
.names n_n48 [19] [34]
01 1
.names [18] [108] [35]
11 1
.names n_n23 n_n47 [36]
00 1
.names n_n47 n_n46 [108]
10 1
.names [18] n_n48 [109]
11 1
.names n_n47 n_n46 [110]
0- 1
-0 1
.names [18] n_n49 [111]
11 1
.names n_n49 n_n48 [112]
01 1
.names n_n49 n_n48 [113]
11 1
.names n_n46 s208_in_9_ [114]
00 1
.names n_n47 n_n46 [115]
00 1
.names n_n49 n_n48 [116]
00 1
.names [115] n_n50 [117]
10 1
.names n_n48 s208_in_4_ [118]
01 1
.names [26] [25] [119]
1- 1
-1 1
.names [15] s208_in_0_ [120]
1- 1
-1 1
.end