vtr_flow/benchmarks/blif/5/mark1.blif

.model top
.inputs mark1_in_0_ mark1_in_2_ mark1_in_1_ mark1_in_4_ mark1_in_3_ clock
.outputs mark1_out_15_ mark1_out_14_ mark1_out_13_ mark1_out_12_ mark1_out_11_ \
mark1_out_9_ mark1_out_7_ mark1_out_8_ mark1_out_5_ mark1_out_6_ mark1_out_3_ \
mark1_out_4_ mark1_out_1_ mark1_out_2_ mark1_out_10_ mark1_out_0_
.latch    n_n54 mark1_out_8_ re clock 2
.latch    n_n55 n_n92 re clock 2
.latch    n_n56 n_n93 re clock 2
.latch    n_n57 n_n94 re clock 2
.names n_n94 mark1_out_15_
0 1
.names mark1_in_4_ mark1_out_8_ n_n92 n_n93 n_n94 mark1_out_14_
0---- 1
-01-- 1
--11- 1
---00 1
.names mark1_in_4_ mark1_out_8_ n_n92 n_n93 n_n94 mark1_out_13_
0---- 1
-1--- 1
--0-- 1
---1- 1
----0 1
.names mark1_out_8_ n_n92 mark1_out_12_
10 1
.names mark1_in_4_ mark1_out_8_ n_n92 n_n93 n_n94 mark1_out_9_
0---- 1
---0- 1
----0 1
-10-- 1
.names mark1_in_4_ n_n92 n_n93 n_n94 mark1_out_7_
1001 1
.names mark1_in_4_ n_n92 n_n93 n_n94 mark1_out_6_
1010 1
.names mark1_out_3_
.names mark1_out_4_
.names n_n92 n_n93 mark1_out_1_
01 1
.names n_n93 mark1_out_2_
0 1
.names mark1_out_10_
 1
.names n_n92 mark1_out_0_
0 1
.names mark1_in_4_ n_n92 n_n94 [42] [184] n_n54
1---1 1
1101- 1
.names mark1_in_4_ [44] n_n55
11 1
.names mark1_in_4_ [47] [48] [189] n_n56
11-- 1
1-1- 1
1--1 1
.names mark1_in_4_ [32] [192] n_n57
11- 1
1-1 1
.names mark1_in_1_ mark1_out_8_ n_n92 n_n93 n_n94 [44]
-11-- 1
--01- 1
---01 1
---10 1
1-10- 1
.names mark1_in_0_ mark1_in_2_ mark1_in_1_ mark1_out_8_ n_n93 [42]
----1 1
00-0- 1
1110- 1
.names n_n92 mark1_out_11_
1 1
.names n_n92 mark1_out_5_
1 1
.names mark1_in_3_ mark1_out_8_ n_n92 n_n93 n_n94 [32]
-110- 1
111-0 1
.names mark1_in_0_ mark1_in_2_ mark1_in_1_ n_n92 n_n93 [47]
---00 1
-00-0 1
011-0 1
.names mark1_in_3_ mark1_out_8_ n_n93 n_n94 [48]
-10- 1
11-0 1
.names mark1_out_8_ n_n92 n_n93 [184]
111 1
100 1
.names mark1_out_8_ n_n92 n_n93 n_n94 [189]
10-- 1
0--1 1
011- 1
.names mark1_in_2_ mark1_in_1_ n_n92 n_n93 n_n94 [192]
--0-1 1
---01 1
0-10- 1
-010- 1
.end