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foss-fpga-tools
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third_party
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vtr-verilog-to-routing
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e826f57b27df591f83a2845a638636875713f938
/
.
/
vtr_flow
/
benchmarks
/
blif
/
7
/
shiftreg.blif
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.
model top
.
inputs shiftreg_in clock
.
outputs shiftreg_out
.
latch shiftreg_in n_n10 re clock
2
.
latch n_n10 n_n11 re clock
2
.
latch n_n11 shiftreg_out re clock
2
.
end
