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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
e826f57b27df591f83a2845a638636875713f938
/
.
/
vtr_flow
/
benchmarks
/
microbenchmarks
/
always_false.blif
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.
model always_false
.
inputs i0 i1 i2 i3 i4 i5
.
outputs o
.
names i0 i1 i2 i3 i4 i5 o
------
0
.
end
