vtr_flow/benchmarks/microbenchmarks/rca_1bit.blif - third_party/vtr-verilog-to-routing - Git at Google

 .model top
 .inputs cin a0 b0
 .outputs s0 cout
 .names b0 a0 cin s0
 001 1
 010 1
 100 1
 111 1
 .names b0 a0 cin cout
 011 1
 101 1
 110 1
 111 1
 .end
	.model top
	.inputs cin a0 b0
	.outputs s0 cout
	.names b0 a0 cin s0
	001 1
	010 1
	100 1
	111 1
	.names b0 a0 cin cout
	011 1
	101 1
	110 1
	111 1
	.end