ODIN_II/regression_test/benchmark/task/syntax/task.conf

########################
# syntax benchmarks config
########################

regression_params=--include_default_arch
simulation_params= -g 2 -L reset rst -H we
script_synthesis_params=--time_limit 3600s --tool valgrind
script_simulation_params=--time_limit 3600s

# setup the architecture
arch_dir=../vtr_flow/arch/timing

arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# setup the circuits
circuit_dir=regression_test/benchmark/verilog/syntax

circuit_list_add=8_bit_for_pass_through_off_by_1.v
circuit_list_add=multi_module_io_data_types.v
circuit_list_add=bm_DL_nbit_adder_with_carryout_and_overflow_simplified.v
circuit_list_add=h7_of_8_bit_for_pass_through.v
circuit_list_add=undeclared_signal.v
circuit_list_add=multi_module.v
circuit_list_add=bm_DL_nbit_adder_with_carryout_and_overflow.v
circuit_list_add=nested-ifdef-syntax.v
circuit_list_add=ifndef-else-syntax.v
circuit_list_add=include-syntax.v
circuit_list_add=8_bit_for_pass_through.v
circuit_list_add=timescale_syntax.v
circuit_list_add=inferred_SPram.v
circuit_list_add=bm_DL_simple_fsm.v
circuit_list_add=8_bit_for_pass_through_module.v
circuit_list_add=not_enough_wires.v
circuit_list_add=bm_jk_rtl.v
circuit_list_add=diffeq_f_systemC.v
circuit_list_add=l2_and_h2_of_8_bit_for_pass_through.v
circuit_list_add=constant_module_inst.v
circuit_list_add=sign_extend_nomem.v
circuit_list_add=diffeq_paj_convert.v
circuit_list_add=flip_flop_enable.v
circuit_list_add=function_syntax.v
circuit_list_add=inferred_DPram.v
circuit_list_add=bm_DL_4_bit_updown_counter.v
circuit_list_add=spram_big.v
circuit_list_add=ifdef-else-syntax.v
circuit_list_add=complex_post_for_loop.v
circuit_list_add=inferred_ram_w_clog2.v
circuit_list_add=flip_flop_enable_w_begin_label.v
circuit_list_add=simple_task.v
circuit_list_add=simple_function.v
circuit_list_add=simple_module.v
circuit_list_add=task_automatic.v
circuit_list_add=task_multiple_instances.v
circuit_list_add=function_automatic.v
circuit_list_add=unconnected_input.v