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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
f98a99ffc7d63c92e4d87d6b024e649c80a4c681
/
.
/
abc
/
src
/
opt
/
sbd
/
module.make
blob: fc176715db6a70d521c633d8b962081619ca7a38 [
file
]
SRC
+=
src
/
opt
/
sbd
/
sbd
.
c \
src
/
opt
/
sbd
/
sbdCnf
.
c \
src
/
opt
/
sbd
/
sbdCore
.
c \
src
/
opt
/
sbd
/
sbdCut
.
c \
src
/
opt
/
sbd
/
sbdCut2
.
c \
src
/
opt
/
sbd
/
sbdLut
.
c \
src
/
opt
/
sbd
/
sbdPath
.
c \
src
/
opt
/
sbd
/
sbdSat
.
c \
src
/
opt
/
sbd
/
sbdWin
.
c