| ######################## |
| # FIR benchmarks config |
| ######################## |
| |
| regression_params=--include_default_arch |
| script_synthesis_params=--time_limit 3600s |
| script_simulation_params=--time_limit 3600s |
| simulation_params= -L reset rst -H we |
| |
| # setup the architecture |
| arch_dir=../vtr_flow/arch/timing |
| |
| arch_list_add=k6_N10_40nm.xml |
| arch_list_add=k6_N10_mem32K_40nm.xml |
| #arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml |
| |
| # setup the circuits |
| circuit_dir=regression_test/benchmark/verilog/FIR |
| |
| circuit_list_add=ex1EP16_fir_6.v |
| circuit_list_add=ex2BT16_fir_71.v |
| circuit_list_add=ex3PM16_fir_61.v |
| circuit_list_add=ex2EP16_fir_13.v |
| circuit_list_add=ex4LS16_fir.v |
| circuit_list_add=ex1PM16_fir_28.v |
| circuit_list_add=ex4PM16_fir_152.v |
| circuit_list_add=ex4EP16_fir_10.v |
| circuit_list_add=ex2PM16_fir_119.v |
| circuit_list_add=ex1LS16_fir_41.v |
| circuit_list_add=ex1BT16_fir_20.v |
| |
