ODIN_II/regression_test/benchmark/task/micro/task.conf

########################
# micro benchmarks config
########################
regression_params=--include_default_arch
script_synthesis_params=--time_limit 3600s --tool valgrind
script_simulation_params=--time_limit 3600s
simulation_params= -L reset rst -H we

# setup the architecture
arch_dir=../vtr_flow/arch/timing

arch_list_add=k6_N10_40nm.xml
arch_list_add=k6_N10_mem32K_40nm.xml
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# setup the circuits
circuit_dir=regression_test/benchmark/verilog/micro

circuit_list_add=bm_DL_logic_w_Dff.v
circuit_list_add=bm_my_D_latch1.v
circuit_list_add=bm_arithmetic_unused_bits.v
circuit_list_add=bm_dag1_log_mod.v
circuit_list_add=bm_DL_2_4_encoder.v
circuit_list_add=bm_match6_str_arch.v
circuit_list_add=bm_dag3_mod.v
circuit_list_add=bm_DL_2_cascaded_flip_flops.v
circuit_list_add=bm_stmt_compare_padding.v
circuit_list_add=bm_and_log.v
circuit_list_add=bm_dag1_mod.v
circuit_list_add=bm_DL_4_1_mux.v
circuit_list_add=bm_DL_4_16_encoder.v
circuit_list_add=bm_match3_str_arch.v
circuit_list_add=bm_dag2_log.v
circuit_list_add=bm_DL_2_1_mux.v
circuit_list_add=parameter_2.v
circuit_list_add=bm_functional_test.v
circuit_list_add=bm_dag3_lpm_log.v
circuit_list_add=bm_dag2_lpm.v
circuit_list_add=bm_DL_4_bit_comparator.v
circuit_list_add=bm_dag3_lpm.v
circuit_list_add=bm_dag4_mod.v
circuit_list_add=bm_DL_D_flipflop.v
circuit_list_add=bm_DL_structural_logic2.v
circuit_list_add=bm_stmt_all_mod.v
circuit_list_add=bm_DL_behavioural_full_adder.v
circuit_list_add=bm_dag1_log.v
circuit_list_add=bm_match4_str_arch.v
circuit_list_add=bm_dag3_lpm_mod.v
circuit_list_add=parameter.v
circuit_list_add=bm_DL_74381_ALU.v
circuit_list_add=bm_DL_4_bit_shift_register.v
circuit_list_add=bm_dag3_log_mod.v
circuit_list_add=bm_match1_str_arch.v
circuit_list_add=bm_DL_Dff_w_synch_reset.v
circuit_list_add=bm_dag2_mod.v
circuit_list_add=bm_lpm_concat.v
circuit_list_add=bm_dag3_log.v
circuit_list_add=bm_match5_str_arch.v
circuit_list_add=bm_add_lpm.v
circuit_list_add=bm_DL_structural_logic.v
circuit_list_add=bm_base_multiply.v
circuit_list_add=bm_mod.v
circuit_list_add=param_override.v
circuit_list_add=bm_dag1_lpm.v
circuit_list_add=bm_DL_logic_w_Dff2.v
circuit_list_add=bm_DL_BCD_adder.v
circuit_list_add=bm_expr_all_mod.v
circuit_list_add=bm_tester.v
circuit_list_add=bm_DL_16_1_mux.v
circuit_list_add=bm_dag2_log_mod.v
circuit_list_add=bm_dag3_lpm_log_mod.v
circuit_list_add=bm_match2_str_arch.v
circuit_list_add=bm_my_D_latch2.v
circuit_list_add=bm_if_reset.v
circuit_list_add=bm_DL_four_bit_adder_continuous_assign.v
circuit_list_add=generate.v
circuit_list_add=bm_DL_BCD_7_segment_without_x.v
circuit_list_add=bm_lpm_all.v
circuit_list_add=bm_if_common.v
circuit_list_add=bm_if_collapse.v
circuit_list_add=case_generate.v
circuit_list_add=if_generate.v

# these require specific architectures to run without errors

# circuit_list_add=adder_hard_block.v
# circuit_list_add=multiply_hard_block.v