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foss-fpga-tools
/
third_party
/
vtr-verilog-to-routing
/
fe12d9429d71f7e8d3cff6eacf150ff37a523a14
/
.
/
abc_with_bb_support
/
JAMIESON_TESTS
/
sample.blif
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.
model sample
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inputs a00 a01 b00 b01
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outputs y00 y01
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names a00 a01 y00
11
1
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names b00 b01 y01
10
1
.
end
