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foss-fpga-tools/third_party/vtr-verilog-to-routing/refs/heads/interposer/./doc/journal/fpgapaperfinal/FPGAPaper/graph_src
tree: 6fa645e357bbddb727e43e546bccae82c7778638 [path history] [tgz]
  1. clique.dot
  2. crit_path_4part.dat
  3. crit_path_4part.plot
  4. graph_topology_cutsize.dat
  5. graph_topology_cutsize.plot
  6. graph_topology_vpr.dat
  7. graph_topology_vpr.plot
  8. packing_bloat.dat
  9. packing_bloat.plot
  10. star.dot
  11. test.plot
  12. vpr_flows.plot
  13. vpr_flows_crit_path.dat
  14. vpr_flows_mcw.dat
  15. wires_cut.dat
  16. wires_cut.plot
  17. wires_cut_4part.dat
  18. wires_cut_4part.plot