Sign in
foss-fpga-tools
/
third_party
/
yosys
/
0221f7e524163f6ffdd4ceae9038187eeeefc3e9
/
.
/
examples
/
intel
/
asicworld_lfsr
/
README
blob: ba365fabf8edb55fc9fa73bfad8011bb36d92910 [
file
] [
log
] [
blame
]
Source
of the files
:
http
:
//www.asic-world.com/examples/verilog/lfsr.html
Run
first
:
runme_presynth
Generate
output netlist
with
run_max10
or
run_cycloneiv
Then
,
check
with
:
runme_postsynth