Common memory test now shared

diff --git a/tests/arch/anlogic/memory.v b/tests/arch/anlogic/memory.v
deleted file mode 100644
index cb7753f..0000000
--- a/tests/arch/anlogic/memory.v
+++ /dev/null

@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule

diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys
index 8c0ce84..87b93c2 100644
--- a/tests/arch/anlogic/memory.ys
+++ b/tests/arch/anlogic/memory.ys

@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/ecp5/memory.v b/tests/arch/common/memory.v
similarity index 100%
rename from tests/arch/ecp5/memory.v
rename to tests/arch/common/memory.v


diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/memory.ys
index 9b475f1..c82b7b4 100644
--- a/tests/arch/ecp5/memory.ys
+++ b/tests/arch/ecp5/memory.ys

@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/efinix/memory.v b/tests/arch/efinix/memory.v
deleted file mode 100644
index 5634d65..0000000
--- a/tests/arch/efinix/memory.v
+++ /dev/null

@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [8:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule

diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys
index fe24b0a..6f6acdc 100644
--- a/tests/arch/efinix/memory.ys
+++ b/tests/arch/efinix/memory.ys

@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/ice40/memory.v b/tests/arch/ice40/memory.v
deleted file mode 100644
index cb7753f..0000000
--- a/tests/arch/ice40/memory.v
+++ /dev/null

@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule

diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys
index a66afba..c356e67 100644
--- a/tests/arch/ice40/memory.ys
+++ b/tests/arch/ice40/memory.ys

@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/xilinx/memory.v b/tests/arch/xilinx/memory.v
deleted file mode 100644
index cb7753f..0000000
--- a/tests/arch/xilinx/memory.v
+++ /dev/null

@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule

diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys
index 5402513..da1ed0e 100644
--- a/tests/arch/xilinx/memory.ys
+++ b/tests/arch/xilinx/memory.ys

@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap