tests/arch/xilinx/xilinx_dff.ys

read_verilog <<EOT
module top(input c, d, r, output reg q);
always @(posedge c)
    if (r) q <= 1'b0;
    else q <= d;
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
design -load postopt
cd top
select -assert-count 1 t:FDRE
select -assert-none t:* t:FDRE %d t:BUFG %d


design -reset
read_verilog <<EOT
module top(input c, d, r, e, output reg q);
always @(posedge c) begin
    if (e) q <= d;
    if (r) q <= 1'b0;
end
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
design -load postopt
cd top
select -assert-count 1 t:FDRE
select -assert-none t:* t:FDRE %d t:BUFG %d


design -reset
read_verilog <<EOT
module top(input c, d, s, output reg q);
always @(posedge c)
    if (s) q <= 1'b1;
    else q <= d;
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
design -load postopt
cd top
select -assert-count 1 t:FDSE
select -assert-none t:* t:FDSE %d t:BUFG %d


design -reset
read_verilog <<EOT
module top(input c, d, e, clr, output reg q);
always @(posedge c or posedge clr)
    if (clr) q <= 1'b0;
    else if (e) q <= d;
endmodule
EOT
proc
equiv_opt -assert -map +/xilinx/cells_sim.v -multiclock synth_xilinx
design -load postopt
cd top
select -assert-count 1 t:FDCE
select -assert-none t:* t:FDCE %d t:BUFG %d