Add async2sync

tests/ecp5/adffs.ys

diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys
index b129419..c6780e5 100644
--- a/tests/ecp5/adffs.ys
+++ b/tests/ecp5/adffs.ys
@@ -3,7 +3,7 @@
 
 hierarchy -top adff
 proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -12,7 +12,7 @@
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -22,7 +22,7 @@
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF
@@ -32,7 +32,7 @@
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:TRELLIS_FF

tests/efinix/adffs.ys

diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys
index 7916264..1069c6c 100644
--- a/tests/efinix/adffs.ys
+++ b/tests/efinix/adffs.ys
@@ -3,7 +3,7 @@
 
 hierarchy -top adff
 proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_FF
@@ -15,7 +15,7 @@
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_FF
@@ -27,7 +27,7 @@
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_FF
@@ -40,7 +40,7 @@
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:EFX_FF