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foss-fpga-tools
/
third_party
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yosys
/
51e4e29bb1f7c030b0cac351c522dc41f7587be2
/
.
/
tests
/
opt
/
opt_rmdff_sat.v
blob: 5a0a6fe3703bf2f43cb23cc7adfe9df0c9160130 [
file
]
module
top
(
input clk
,
output reg
[
7
:
0
]
cnt
);
initial cnt
=
0
;
always
@(
posedge clk
)
begin
if
(
cnt
<
20
)
cnt
<=
cnt
+
1
;
else
cnt
<=
0
;
end
endmodule