manual/PRESENTATION_ExSyn/proc_02.v - third_party/yosys - Git at Google

 module test(input D, C, R, RV,
             output reg Q);
     always @(posedge C, posedge R)
         if (R)
 	    Q <= RV;
 	else
 	    Q <= D;
 endmodule
	module test(input D, C, R, RV,
	output reg Q);
	always @(posedge C, posedge R)
	if (R)
	Q <= RV;
	else
	Q <= D;
	endmodule