Sign in
foss-fpga-tools
/
third_party
/
yosys
/
55bda2b2c693a7ff79da545e7b52901de00df475
/
.
/
tests
/
errors
/
syntax_err09.v
blob: 1e472eb94ae9d0283aecd18824b50d5e458ea338 [
file
]
module
a
(
input wire x
=
1
'b0);
endmodule
