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foss-fpga-tools
/
third_party
/
yosys
/
5603595e5c0efd2afc9ba810e6e5992e5d81d44c
/
.
/
tests
/
arch
/
common
/
dffs.v
blob: 3418787c9fbf25125d0e79cf11065d279df064a6 [
file
]
module
dff
(
input d
,
clk
,
output reg q
);
always
@(
posedge clk
)
q
<=
d
;
endmodule
module
dffe
(
input d
,
clk
,
en
,
output reg q
);
initial
begin
q
=
0
;
end
always
@(
posedge clk
)
if
(
en
)
q
<=
d
;
endmodule