| read_verilog <<EOT | |
| module sub(input i, output o, input j); | |
| foobar _TECHMAP_REPLACE_(i, o, j); | |
| wire _TECHMAP_REPLACE_.asdf = i ; | |
| barfoo _TECHMAP_REPLACE_.blah (i, o, j); | |
| endmodule | |
| EOT | |
| design -stash techmap | |
| read_verilog <<EOT | |
| module top(input i, output o); | |
| sub s0(i, o); | |
| endmodule | |
| EOT | |
| techmap -map %techmap | |
| select -assert-any w:s0.asdf | |
| select -assert-any c:s0.blah |