Do not sigmap keep bits inside write_xaiger
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 8513611..97fec93 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc
@@ -168,7 +168,7 @@ } if (keep) - keep_bits.insert(bit); + keep_bits.insert(wirebit); if (wire->port_input || keep) { if (bit != wirebit)