Brackets

passes/techmap/clkpart.cc

diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc
index 4fa7292..bf3b5bd 100644
--- a/passes/techmap/clkpart.cc
+++ b/passes/techmap/clkpart.cc
@@ -144,7 +144,7 @@
 				{
 					bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
 					bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
-					key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E)) : RTLIL::SigSpec()));
+					key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec());
 				}
 				else
 					continue;