sv: Improve handling of wildcard port connections

Signed-off-by: David Shah <dave@ds0.me>

frontends/verilog/verilog_lexer.l

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index f4a0484..4a3090a 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -431,7 +431,7 @@
 "+:" { return TOK_POS_INDEXED; }
 "-:" { return TOK_NEG_INDEXED; }
 
-".*" { return TOK_AUTOCONNECT_ALL; }
+".*" { return TOK_WILDCARD_CONNECT; }
 
 [-+]?[=*]> {
 	if (!specify_mode) REJECT;

frontends/verilog/verilog_parser.y

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 1758354..2cb408e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -138,7 +138,7 @@
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
-%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL
+%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
@@ -1581,8 +1581,10 @@
 		delete $3;
 		free_attr($1);
 	} |
-	attr TOK_AUTOCONNECT_ALL {
-		astbuf2->attributes[ID(implicit_port_conns)] = AstNode::mkconst_int(1, false);
+	attr TOK_WILDCARD_CONNECT {
+		if (!sv_mode)
+			frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
+		astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false);
 	};
 
 always_comb_or_latch:

passes/hierarchy/hierarchy.cc

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index c298a66..fa4a8ea 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -992,7 +992,7 @@
 					if (wire->port_input && wire->attributes.count("\\defaultvalue"))
 						defaults_db[module->name][wire->name] = wire->attributes.at("\\defaultvalue");
 		}
-		// Process SV implicit port connections
+		// Process SV implicit wildcard port connections
 		std::set<Module*> blackbox_derivatives;
 		std::vector<Module*> design_modules = design->modules();
 
@@ -1000,7 +1000,7 @@
 		{
 			for (auto cell : module->cells())
 			{
-				if (!cell->get_bool_attribute(ID(implicit_port_conns)))
+				if (!cell->get_bool_attribute(ID(wildcard_port_conns)))
 					continue;
 				Module *m = design->module(cell->type);
 
@@ -1042,7 +1042,7 @@
 								RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 					cell->setPort(wire->name, parent_wire);
 				}
-				cell->attributes.erase(ID(implicit_port_conns));
+				cell->attributes.erase(ID(wildcard_port_conns));
 			}
 		}