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yosys
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8b68a939f451731cc82fd03b1048d9aab471f47b
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.
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tests
/
asicworld
/
code_tidbits_syn_reset.v
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module
syn_reset
(
clk
,
reset
,
a
,
c
);
input clk
;
input reset
;
input a
;
output c
;
wire clk
;
wire reset
;
wire a
;
reg c
;
always
@
(
posedge clk
)
if
(
reset
==
1
'b1) begin
c <= 0;
end else begin
c <= a;
end
endmodule