tests/asicworld/code_verilog_tutorial_multiply.v - third_party/yosys - Git at Google

 module muliply (a,product);
   	  	input [3:0] a;
   	  	output [4:0] product;
   	  	wire [4:0] product;

   	  	assign product  = a << 1;

 endmodule
	module muliply (a,product);
	input [3:0] a;
	output [4:0] product;
	wire [4:0] product;

	assign product = a << 1;

	endmodule